1. Field of the Invention
The present invention relates to a semiconductor device having a surrounding gate MOS transistor (SGT) and a method for manufacturing the semiconductor device.
2. Description of the Related Art
Recently, the use of SGTs has been increasing as semiconductor elements that provide highly integrated semiconductor devices. With this increase in the use, high-speed driving of semiconductor devices having SGTs has further been desired.
FIG. 8 shows a typical example of a complementary metal-oxide-semiconductor (CMOS) inverter circuit having metal-oxide-semiconductor (MOS) transistors. As shown in FIG. 8, this circuit includes an N-channel MOS transistor 100a and a P-channel MOS transistor 100b. A gate 101a of the N-channel MOS transistor 100a and a gate 101b of the P-channel MOS transistor 100b are connected to an input terminal Vi. A drain 102a of the N-channel MOS transistor 100a and a drain 102b of the P-channel MOS transistor 100b are connected to an output terminal Vo. A source 103b of the P-channel MOS transistor 100b is connected to a power supply wiring metal layer Vdd. A source 103a of the N-channel MOS transistor 100a is connected to a ground terminal Vss. In this circuit, in response to the application of an input voltage corresponding to “1” or “0” to the input terminal Vi, an output voltage corresponding to “0” or “1” that is inverted from the input voltage is taken out from the output terminal Vo. Such CMOS inverter circuits are used in various circuit chips such as microprocessors. The realization of high-speed driving of circuits using CMOS inverter circuits has been desired.
FIG. 9 is a cross-sectional view of a planar CMOS inverter circuit in the related art. As shown in FIG. 9, an N-well region 105 (hereinafter, a semiconductor region that forms a P-channel MOS transistor and contains a donor impurity is referred to as “N-well region”) is formed in a P-type semiconductor substrate 104 (hereinafter, a semiconductor substrate containing an acceptor impurity is referred to as “P-type semiconductor substrate”). Element isolation insulating layers 106a and 106b are each formed between a surface layer portion of the N-well region 105 and a surface layer portion of the P-type semiconductor substrate 104. A gate oxide film 107a for a P-channel MOS transistor is formed on a surface of the N-well region 105, and a gate oxide film 107b for an N-channel MOS transistor is formed on a surface of the P-type semiconductor substrate 104. A gate conductor layer 108a for the P-channel MOS transistor and a gate conductor layer 108b for the N-channel MOS transistor are respectively formed on the gate oxide film 107a and the gate oxide film 107b. 
Furthermore, as shown in FIG. 9, a P−region 141a doped with a low concentration of an acceptor impurity (hereinafter, a semiconductor region containing a low concentration of an acceptor impurity is referred to as “P−region”) is formed in a surface layer portion of the N-well region 105 on both the right-hand side and the left-hand side of the gate conductor layer 108a for the P-channel MOS transistor. Similarly, an N−region 141b doped with a low concentration of a donor impurity (hereinafter, a semiconductor region containing a low concentration of a donor impurity is referred to as “N−region”) is formed on both sides of the gate conductor layer 108b for the N-channel MOS transistor. A sidewall insulating layer 142a is formed on the N-well region 105 on both sides of the gate conductor layer 108a. A sidewall insulating layer 142b is formed on the P-type semiconductor substrate 104 on both sides of the gate conductor layer 108b. A source P+ region 109a (hereinafter, a semiconductor region containing a high concentration of an acceptor impurity is referred to as “P+ region”) and a drain P+ region 109b of the P-channel MOS transistor are formed on both sides of the gate conductor layer 108a. A source N+ region 110b (hereinafter, a semiconductor region containing a high concentration of a donor impurity is referred to as “N+ region”) and a drain N+ region 110a are formed in surface layer portions of the P-type semiconductor substrate 104. Silicide layers 143a, 143b, 143c, and 143d are formed in surface layer portions of the source P+ region 109a and the drain P+ region 109b and surface layer portions of the drain N+ region 110a and the source N+ region 110b, respectively. A first interlayer insulating layer 111 is formed on the N-well region 105 and the P-type semiconductor substrate 104. Contact holes 112a, 112b, 112c, and 112d are respectively formed above the source P+ region 109a and the drain P+ region 109b and above the drain N+ region 110a and the source N+ region 110b with the silicide layers 143a, 143b, 143c, and 143d therebetween so as to penetrate the first interlayer insulating layer 111.
As shown in FIG. 9, a power supply wiring metal layer Vdd formed on the first interlayer insulating layer 111 is connected to the source P+ region 109a of the P-channel MOS transistor through the contact hole 112a. An output wiring metal layer Vo formed on the first interlayer insulating layer 111 is connected to the drain P+ region 109b of the P-channel MOS transistor through the contact hole 112b. The output wiring metal layer Vo is connected to the drain N+ region 110a of the N-channel MOS transistor through the contact hole 112c. A ground wiring metal layer Vss is connected to the source N+ region 110b of the N-channel MOS transistor through the contact hole 112d. A second interlayer insulating layer 113 is formed on the first interlayer insulating layer 111. Contact holes 114a and 114b are respectively formed on the gate conductor layer 108a for the P-channel MOS transistor and the gate conductor layer 108b for the N-channel MOS transistor so as to penetrate the first interlayer insulating layer 111 and the second interlayer insulating layer 113. An input wiring metal layer Vi formed on the second interlayer insulating layer 113 is connected to the gate conductor layer 108a for the P-channel MOS transistor through the contact hole 114a. The input wiring metal layer Vi is connected to the gate conductor layer 108b for the N-channel MOS transistor through the contact hole 114b. 
High-speed driving of many CMOS circuits including the planar CMOS inverter circuit shown in FIG. 9 has been further required. In order to realize high-speed driving of CMOS circuits, it is necessary to reduce the resistances of the drain N+ region 110a and the source N+ region 110b of the N-channel MOS transistor and the resistances of the source P+ region 109a and the drain P+ region 109b of the P-channel MOS transistor. For this purpose, the silicide layers 143a and 143b that are respectively formed on the source P+ region 109a and the drain P+ region 109b need to be formed so as to be close to the gate conductor layer 108a as much as possible. Similarly, the silicide layers 143c and 143d that are respectively formed on the drain N+ region 110a and the source N+ region 110b need to be formed so as to be close to the gate conductor layer 108b as much as possible. In general, a signal propagation speed of a circuit is controlled by the product RC of the resistance (R) and the capacitance (C). Accordingly, in addition to the reduction in the resistances of the drain N+ region 110a and the source N+ region 110b of the N-channel MOS transistor and the reduction in the resistances of the source P+ region 109a and the drain P+ region 109b of the P-channel MOS transistor, the coupling capacitance between the gate conductor layer 108a and the source P+ and drain P+ regions 109a and 109b is reduced by providing the sidewall insulating layer 142a between the gate conductor layer 108a and the source P+ and drain P+ regions 109a and 109b, and the coupling capacitance between the gate conductor layer 108b and the drain N+ and source N+ regions 110a and 110b is reduced by providing the sidewall insulating layer 142b between the gate conductor layer 108b and the drain N+ and source N+ regions 110a and 110b. Furthermore, it is necessary to realize the reduction in the resistances of the drain N+ region 110a, the source N+ region 110b, the source P+ region 109a, and the drain P+ region 109b, the reduction in the coupling capacitance between the gate conductor layer 108a and the source P+ and drain P+ regions 109a and 109b, and the reduction in the coupling capacitance between the gate conductor layer 108b and the drain N+ and source N+ regions 110a and 110b with a good controllability. In addition, with the realization of a high density of the planar CMOS inverter circuit shown in FIG. 9, the sizes of the drain N+ region 110a and the source N+ region 110b of the N-channel MOS transistor and the sizes of the source P+ region 109a and the drain P+ region 109b of the P-channel MOS transistor have been reduced. Therefore, improvements for realizing further reduction in the resistances and further reduction in the coupling capacitances of the drain N+ region 110a and the source N+ region 110b of the N-channel MOS transistor and the source P+ region 109a and the drain P+ region 109b of the P-channel MOS transistor have been required.
In planar MOS transistors, channels of a P-channel MOS transistor and an N-channel MOS transistor are formed between a source and a drain in a horizontal direction along the surfaces of the P-type semiconductor substrate 104 and the N-well region 105, respectively. In contrast, channels of SGTs are formed in a direction perpendicular to a surface of a semiconductor substrate (refer to, for example, Japanese Unexamined Patent Application Publication No. 2-188966 and Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991))
FIG. 10 is a structural schematic view of an N-channel SGT. N+ regions 116a and 116b are formed in upper and lower portions of a P-type or i-type (intrinsic) Si pillar 115 (hereinafter, a silicon semiconductor pillar is referred to as “Si pillar”). When one of the N+ regions 116a and 116b functions as a source, the other functions as a drain. When one of the N+ regions 116a and 116b functions as a drain, the other functions as a source. The Si pillar 115 located between the source/drain N+ regions 116a and 116b functions as a channel region 117. A gate insulating layer 118 is formed so as to surround the channel region 117. A gate conductor layer 119 is formed so as to surround the gate insulating layer 118. In the SGT, the source/drain N+ regions 116a and 116b, the channel region 117, the gate insulating layer 118, and the gate conductor layer 119 are formed in or on the single Si pillar 115. Therefore, the occupation area of the surface of the SGT apparently corresponds to the occupation area of a single source or drain N+ region of a planar MOS transistor. Accordingly, regarding circuit chips including SGTs, a further reduction in the chip size can be realized compared with circuit chips including planar MOS transistors.
FIG. 11 is a cross-sectional view of a CMOS inverter circuit having SGTs (refer to, for example, U.S. Patent Application Publication No. 2010/0264484). An i-layer 121 (the term “i-layer” refers to an intrinsic Si layer) is formed on an insulating layer substrate 120. A Si pillar SP1 for a P-channel SGT and a Si pillar SP2 for an N-channel SGT are formed on the i-layer 121. A drain P+ region 122 of the P-channel SGT is formed in the i-layer 121 connected to a lower portion of the Si pillar SP1 for the P-channel SGT so as to be integrated with the i-layer 121 and to surround a lower portion of the Si pillar SP1. Similarly, a drain N+ region 123 of the N-channel SGT is formed so as to be integrated with the i-layer 121 and to surround a lower portion of the Si pillar SP2. Furthermore, a source P+ region 124 of the P-channel SGT is formed in an upper portion of the Si pillar SP1 for the P-channel SGT. Similarly, a source N+ region 125 of the N-channel SGT is formed in an upper portion of the Si pillar SP2 for the N-channel SGT.
Furthermore, as shown in FIG. 11, gate insulating layers 126a and 126b are formed so as to surround the Si pillars SP1 and SP2, respectively. A gate conductor layer 127a of the P-channel SGT and a gate conductor layer 127b of the N-channel SGT are formed so as to surround the gate insulating layers 126a and 126b, respectively. Sidewall nitride films 128a and 128b which are insulating layers are formed so as to surround the gate conductor layers 127a and 127b, respectively. Similarly, sidewall nitride films 128c and 128d which are insulating layers are respectively formed so as to surround the P+ region of a top portion of the Si pillar SP1 and the N+ region of a top portion of the Si pillar SP2. The drain source P+ region 122 of the P-channel SGT is connected to the drain N+ region 123 of the N-channel SGT through a silicide layer 129d. A silicide layer 129a is formed on the source P+ region 124 of the P-channel SGT. A silicide layer 129c is formed on the source N+ region 125 of the N-channel SGT. Furthermore, silicide layers 129b and 129e are formed on a top portion of the gate insulating layer 126a and a top portion of the gate insulating layer 126b, respectively. An i-layer 130a between the P+ regions 122 and 124 that are respectively located in a lower portion and an upper portion of the Si pillar SP1 functions as a channel of the P-channel SGT. An i-layer 130b between the N+ regions 123 and 125 that are respectively located in a lower portion and an upper portion of the Si pillar SP2 functions as a channel of the N-channel SGT.
As shown in FIG. 11, a SiO2 layer 131 is formed by chemical vapor deposition (CVD) so as to cover the insulating layer substrate 120, the i-layer 121, and the Si pillars SP1 and SP2. Furthermore, contact holes 132a, 132b, and 132c are respectively formed in the SiO2 layer 131 on the Si pillar SP1, the drain P+ region 122 of the P-channel SGT and the drain N+ region 123 of the N-channel SGT, and the Si pillar SP2. A power supply wiring metal layer Vdd formed on the SiO2 layer 131 is connected to the source P+ region 124 of the P-channel SGT and the silicide layer 129a through the contact hole 132a. An output wiring metal layer Vo formed on the SiO2 layer 131 is connected to the drain P+ region 122 of the P-channel SGT, the drain N+ region 123 of the N-channel SGT, and the silicide layer 129d through the contact hole 132b. Furthermore, a ground wiring metal layer Vss formed on the SiO2 layer 131 is connected to the source N+ region 125 of the N-channel SGT and the silicide layer 129c through the contact hole 132c. Furthermore, the gate conductor layer 127a of the P-channel SGT and the gate conductor layer 127b of the N-channel SGT are connected to an input wiring metal layer (not shown) in a state where the gate conductor layers 127a and 127b are connected to each other. In this inverter circuit having SGTs, the P-channel SGT and the N-channel SGT are respectively formed in the Si pillar SP1 and the Si pillar SP2. Therefore, the circuit area when the inverter circuit is viewed in plan view from the vertical direction is reduced. As a result, the size of the inverter circuit can be further reduced as compared with an inverter circuit having planar MOS transistors in the related art.
In the CMOS circuit having SGTs and shown in FIG. 11, high-speed driving of the circuit has been further required as in the inverter circuit having planar CMOS transistors in the related art. To realize high-speed driving of this circuit, a reduction in the resistances of the P+ region 122 and N+ region 123 functioning as a drain and a reduction in the resistances of the P+ region 124 and N+ region 125 functioning as a source is necessary. The P+ regions 122 disposed in a lower portion of the Si pillar SP1 and the N+ region 123 disposed in a lower portion of the Si pillar SP2 are connected to the output wiring metal layer Vo through the silicide layer 129d disposed on outer peripheries of the Si pillars SP1 and SP2 and having a relatively large occupation area. On the other hand, the P+ region 124 disposed in the top portion of the Si pillar SP1 is connected to the power supply wiring metal layer Vdd through the silicide layer 129a formed on a surface of the top portion of the P+ region 124 and having a relatively small occupation area. Similarly, the N+ region 125 disposed in the top portion of the Si pillar SP2 is connected to the ground wiring metal layer Vss through the silicide layer 129c formed on a surface of the top portion of the N+ region 125 and having a relatively small occupation area. Therefore, when the density of the circuit is further increased, the diameters (widths) of the Si pillars SP1 and SP2 are reduced accordingly. As a result, a problem of an increase in the resistances of the P+ region 124 and the N+ region 125 occurs.
In general, a signal propagation speed of a circuit is controlled by the product RC of the resistance (R) and the capacitance (C). Accordingly, it is necessary to reduce not only the resistances of the P+ region 124 and the N+ region 125 that are respectively disposed on the top portions of the Si pillars SP1 and SP2 but also the coupling capacitances between the P+ region 124 and the gate conductor layer 127a and between the N+ region 125 and the gate conductor layer 127b. Furthermore, it is also necessary to provide a structure for realizing, with a good controllability, the reduction in the resistances of the P+ region 124 and the N+ region 125 and the reduction in the coupling capacitances between the P+ region 124 and the gate conductor layer 127a and between the N+ region 125 and the gate conductor layer 127b. 
With regard to the reduction in the resistances of a source and a drain in top portions of Si pillars SP1 and SP2, for example, Japanese Unexamined Patent Application Publication Nos. 2011-40421 and 2004-186601 disclose technologies that the resistances of a source and a drain of SGTs are reduced by connecting side faces of impurity regions to lead-out wirings, the impurity regions being formed in top portions of Si pillars SP1 and SP2 and functioning as a source or a drain. In these technologies, the relationship of a lower position of a side face of a Si pillar where a lead-out wiring is connected to an impurity region, a position of an end of a source or drain impurity region that is in contact with a channel region, and a position of an upper end of a gate conductor layer is not determined by a self-alignment in which, when the position of the upper end of the gate conductor layer is determined, the position of the end of the source or and drain impurity region is determined. Accordingly, it is necessary to realize, with a good controllability, a reduction in the resistances of the source and the drain and a reduction in the coupling capacitances between the impurity region functioning as the source and the gate conductor layer and between the impurity region functioning as the drain and the gate conductor layer. In addition, in Japanese Unexamined Patent Application Publication No. 2011-40421, a thickness of a wiring metal layer connected to an impurity region in a side face of a Si pillar is equal to a thickness of a gate insulating layer. With an increase in the density of the circuit, the thickness of the gate insulating layer is reduced to 2 to 3 nm. Accordingly, in this case, it may be technically difficult to embed the wiring metal layer in a contact hole and the resistance of this wiring metal layer having a small thickness may increase.